I. Field of the Disclosure
The technology of the disclosure relates generally to delay circuits, and particularly to delay circuits for devices that receive a clock signal from a data bus.
II. Background
Electronic devices, such as mobile phones and computer tablets, have become common in contemporary society for supporting various everyday uses. These electronic devices each commonly include a microphone and speakers. Typical microphones and speakers used in electronic devices have analog interfaces, requiring dedicated two (2) port wiring to connect each device. However, electronic devices may include multiple audio devices, such as multiple microphones and/or speakers. Thus, it may be desired to allow for a microprocessor or other control device in such electronic devices to be able to communicate audio data to multiple audio devices over a common communications bus. Further, it may also be desired to provide a defined communications protocol for transporting digital data relating to audio channels to different audio devices in an electronic device over a common communications bus.
In this regard, the MIPI® Alliance has announced SoundWire™ as a communications protocol for transporting digital data relating to audio channels to different audio devices associated with an electronic device. In SoundWire™, one SoundWire™ master interface allows a master electronic device (“master device”), or monitor communicatively coupled thereto, to communicate over a common communications bus with one or more slave electronic devices (“slave devices”) coupled to SoundWire™ slave interfaces. As of this writing, the current version of SoundWire™ is revision 0.6-r02, which was made internally available on May 6, 2014 to MIPI Alliance members through the MIPI sharepoint file server.
The common communications bus in SoundWire™ includes two separate wires: a common data wire (“DATA”) and a common clock wire (“CLK”). In an attempt to provide a low power consumption environment, the SoundWire™ protocol employs a modified Non Return to Zero Inverted (“NRZI”) encoding scheme in conjunction with a double data rate (“DDR”), wherein DATA is examined, and potentially driven, upon every transition of a clock signal on CLK. Employing a NRZI encoding scheme with DDR in this manner affects signaling such that the SoundWire™ protocol suggests a need for a delay circuit in each slave device to avoid data hazards caused by improper signal timing. However, delay circuits that provide the delay necessary for a slave device to avoid data hazards typically generate approximate delays while consuming area and power within the slave device. Therefore, it would be advantageous to provide a more accurate delay to a slave device so as to avoid data hazards, while also reducing area and power consumption of a corresponding delay circuit.